Embedded Systems

Konstantin Lübeck

Photo of Lübeck, Konstantin

Konstantin Lübeck
Universität Tübingen
Fachbereich Informatik
Lehrstuhl Eingebettete Systeme
Sand 13
72076 Tübingen

Telefon
+49 - (0) 70 71 - 29 - 78998
Telefax
+49 - (0) 70 71 - 29 - 50 62
E-Mail
Mail
Büro
Sand 13, B225
Sprechstunde
Open Door Policy

Projekte auf Github

Profil auf Linkedin

Konstantin Lübeck is a graduate research assistant at the Chair for Embedded Systems of the University of Tübingen. He received B.Sc. and M.Sc. degrees in Computer Science from the University of Tübingen in 2015 and 2018 respectively with a major focus on computer engineering and embedded systems. In 2016, he studied at the Uppsala University as an Erasmus exchange student. In 2017, he received a scholarship for master’s thesis from the Stiftung Industrieforschung. Since 2018, he is a lecturer of computer architecture for the Bosch Learning Company initiative at the technology transfer center Tübingen. In addition to his academic work, he is a trained mechatronics technician (certified by the German chamber of industry and commerce, IHK) and worked as a self-employed software developer.

Research Interests

Modeling, evaluation, and prediction of machine learning accelerator performance (end-to-end latency, throughput, roofline) using analytical models based on computer architecture descriptions (from register-transfer level to abstract block diagrams) and deep neural network parameters (layer types and their hyperparameters) for fast design space explorations used in neural network-hardware co-design algorithms.

Veröffentlichungen

Forschungsprojekte

Lehre

Advanced Topics in Embedded Systems Summer 2019
Efficient Machine Learning in Hardware Summer 2021 Summer 2022
Entwurf und Synthese Eingebetteter Systeme Summer 2019
Moderne Architekturen Eingebetteter Systeme Winter 2018 Winter 2019 Winter 2020
Parallele Rechnerarchitekturen Summer 2020 Summer 2021 Winter 2022 Winter 2023
Proseminar: Moderne Architekturen Eingebetteter Systeme Winter 2021
Teamprojekt: Implementierung einer RISC-V Rechnerarchitektur Winter 2024
Teamprojekt: Interaktiver Rechnerarchitektursimulator Summer 2023

Abschlussarbeiten

Aktuelles

Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices

The paper “Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices” has been accepted at the 25th Euromicro Conference on Digital System Design (DSD), pages 1-8, 2022. Keywords: Machine Learning, Neural Networks, AutoML, Neural Architecture Search

Weiterlesen …

Scale4Edge - Skalierbare Infrastruktur für Edge-Computing

Neues BMBF-Projekt in der Informatik der Universität Tübingen zur Entwicklung und Bereitstellung eines Ökosystems für eine skalierbare und flexibel erweiterbare Edge-Computing-Plattform basierend auf der freien RISC-V-Instruktionssatzarchitektur.

Weiterlesen …

GENIAL! - Gemeinsame Elektronik-Roadmap für Innovationen der automobilen Wertschöpfungskette

Neues BMBF-Projekt in der Informatik der Universität Tübingen zur Erstellung einer automotive Innovations-Roadmap. BMBF und Industrie fördern Vorhaben mit insgesamt 19,6 Millionen Euro.

Weiterlesen …